Script Valley
Interview Prep: System Design Rounds
Caching Systems/Assessment

Practice & Assessment

Test your understanding of Caching Systems

Multiple Choice Questions

5
1

In cache-aside pattern, what happens on a cache miss?

2

Which eviction policy is most appropriate for a cache storing trending news articles that were heavily accessed 6 hours ago but are now rarely accessed?

3

What is a cache stampede and what causes it?

4

When would you choose write-back caching over write-through caching?

5

What is the 'hot key problem' in a distributed cache and one solution?

Coding Challenges

1
1

LRU Cache with TTL Support

Implement an LRU cache with TTL (time-to-live) support. The cache must support: put(key, value, ttl_seconds) — store key with value and expiry; get(key) — return value if exists and not expired, else return -1; delete(key) — explicitly remove a key; size() — return number of non-expired keys. Capacity is set at construction. When capacity is reached, evict the least recently ACCESSED (not inserted) key, skipping already-expired keys first. If all slots are expired, clear them and insert the new item. Do not use external libraries except for standard language date/time utilities. Test with: capacity=3, insert A(ttl=10), B(ttl=5), C(ttl=10), get(A), insert D — expect B evicted (expired OR LRU). Estimated time: 25 minutes.

Medium

Mini Project

1

Multi-Layer Cache Simulator

Build a multi-layer cache simulator with three layers: L1 (in-process, capacity 10, LRU eviction), L2 (Redis-like, capacity 100, TTL-based), L3 (simulated database with 50ms artificial delay). When a get(key) is called: check L1 first (instant), then L2 (5ms delay), then L3 (50ms delay). On a miss at any layer, populate all higher layers. Implement cache-aside write pattern: put(key, value) only writes to L3 initially. Add a stats() method that returns: L1 hit rate, L2 hit rate, L3 hit rate, average latency per request. Simulate 1000 requests using a Zipfian distribution (20% of keys get 80% of traffic). Print the stats after simulation. The simulator should prove that a warm multi-layer cache achieves significantly lower average latency than a single cache layer.

Hard